1. Field of the Disclosure
The present disclosure relates to integrated memory devices and particularly to integrated memory devices having a data write assist scheme that provides a reliable data write access to the memory cells through a bitline.
2. Description of the Related Art
Integrated memory devices such as static random access memory devices (SRAMs) are subject to random variations due to Random Dopant Fluctuation (RDF), systematic and parametric variations when manufactured using subnanometer technologies. It is difficult to write data into the memory cells in cross corner locations due to such variations in the memory cell transistors. Such impacts may affect SRAMs manufactured using technologies having a 20 nanometer feature size and less.
For SRAMs in nanometer technologies, write assist concepts may be used to enhance the signal-to-noise margin when writing data into a static memory cell. One way of providing the write assist is to use a negative bitline scheme that applies a negative potential to a bitline when a corresponding data value is supplied by the bitline to a static memory cell. Conventional negative bitline schemes require considerable area and consume considerable power in the integrated circuit, and thus, are less suitable for low power applications. Furthermore, write assist schemes may be designed for a predetermined supply power range and are inflexible to accommodate varying supply power ranges.